1. Technical Field
This disclosure relates to semiconductor layouts and more particularly, to a layout for semiconductor memory cells with vertical transistors.
2. Description of the Related Art
In semiconductor memory devices, gate conductors are formed through a memory array to activate access transistors for reading and writing to storage nodes disposed in deep trenches by charging or discharging the storage node. In prior art systems, access transistors are disposed on a surface of the chip and require a large amount of chip area. These memory cells with planar transistors are activated by a line conductor that forms a gate conductor for the planar transistor. The line width of this gate conductor was critical for these prior art memory cell designs since the line width also defined the gate length for the transistor.
Since the gate conductor (GC) typically has a high electrical resistance (it is generally formed from polysilicon and tungsten silicide), methods were implemented to improve usage of the gate conductor due to it high resistance. One way to address the high resistance of the gate conductor is to form a stitched or bridged pattern. The stitched pattern includes alternating the gate conductors between metal layers to bring the line resistance to a lower level. This reduces the line resistance to a tenth of the gate conductor value.
With the transition to vertical transistors to reduce layout area for memory cells, the gate conductor layer is only used for wiring purposes, and the gate conductor is no longer used to define the gate length. Therefore, the gate conductor width is no longer critical.
Therefore, a need exists for improved layouts and wiring schemes which take advantage of the gate conductor orientation for vertical transistors.